The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 1998
Filed:
Dec. 23, 1994
Applicant:
Inventors:
Robert S Chau, Beaverton, OR (US);
Chan-Hong Chern, Portland, OR (US);
Chia-Hong Jan, Portland, OR (US);
Kevin R Weldon, Portland, OR (US);
Paul A Packan, Beaverton, OR (US);
Leopoldo D Yau, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
257344 ; 257 19 ; 257 65 ; 257336 ; 257377 ; 257382 ; 257385 ; 257408 ; 257742 ; 257755 ; 257773 ; 437 41 ; 437 43 ; 437 90 ; 437101 ; 437162 ; 437189 ; 437191 ; 437192 ; 437203 ; 437228 ; 437233 ; 437913 ;
Abstract
A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip region comprising an ultra shallow region which extends beneath the gate electrode and a raised region.
Chau, Robert. (1998). Transistor with ultra shallow tip and method of fabrication (U.S. Patent No. 5710450). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5710450
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile