The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 1998
Filed:
May. 26, 1995
Hiroshi Toyoda, Kokohama, JP;
Hisashi Kaneko, Fujisawa, JP;
Masahiko Hasunuma, Yokohama, JP;
Takashi Kawanoue, Yokohama, JP;
Hiroshi Tomita, Hadano, JP;
Akihiro Kajita, Yokohama, JP;
Masami Miyauchi, Yokohama, JP;
Takashi Kawakubo, Yokohama, JP;
Sachiyo Ito, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kanagawa-ken, JP;
Abstract
An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary. A method for manufacturing an electronic part, comprising the step of depositing a conductor layer which is mainly formed of one selected from Al and Cu on a substrate via an insulative layer, a barrier layer, a contact layer or an amorphous thin film layer wherein one element selected from Ga, In, Cd, Bi, Pb, Sn and Tl is supplied before or during the deposition of the conductor layer.