The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 23, 1997
Filed:
Jun. 02, 1995
Shuji Ikeda, Koganei, JP;
Satoshi Meguro, Hinoda-machi, JP;
Soichiro Hashiba, Hamura-machi, JP;
Isamu Kuramoto, Higashiyamato, JP;
Atsuyoshi Koike, Kokubunji, JP;
Katsuro Sasaki, Fuchuu, JP;
Koichiro Ishibashi, Tokyo, JP;
Toshiaki Yamanaka, Iruma, JP;
Naotaka Hashimoto, Hachioji, JP;
Nobuyuki Moriwaki, Kyoto, JP;
Shigeru Takahashi, Hitachiohta, JP;
Atsushi Hiraishi, Ohme, JP;
Yutaka Kobayashi, Katsuta, JP;
Seigou Yukutake, Hitachi, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A method is provided for manufacturing a semiconductor integrated circuit device which includes a capacitor element having a first electrode, a second electrode, and a dielectric film formed between said first electrode and said second electrode. In particular, the method includes the step of forming at least one of the first electrode and second electrode with a polycrystalline silicon film which is deposited over a semiconductor substrate by a CVD method and which is doped with an impurity during said deposition to decrease the resistance of the polycrystalline silicon film. The capacitor element formed by this method is particularly useful for memory cells of static random access memory devices.