The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 1997

Filed:

Dec. 22, 1995
Applicant:
Inventors:

Harshvardhan P Sharangpani, Santa Clara, CA (US);

Kent G Fielden, Sunnyvale, CA (US);

Hans J Mulder, San Francisco, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395393 ; 395394 ; 395800 ;
Abstract

A processor microarchitecture for efficient dynamic instruction scheduling and execution. The invention includes a predetermined number of independent dispatch queues. The invention also includes a cluster of execution units coupled to each dispatch queue such that the dispatch queue and the corresponding cluster of execution units forms an independent micropipeline. Chain-building and steering logic coupled to the dispatch queues identifies a consumer instruction relying on a producer instruction for an operand, and issues the consumer instruction to the same dispatch queue as the producer instruction that it is dependent upon. The instructions are issued from the dispatch queue to the corresponding cluster of execution units. In one embodiment, the output of each execution unit in the cluster is routed to the inputs of all execution units in the cluster such that the result of executing the producer instruction is readily available as an operand for execution of the consumer instruction.


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