The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 1997
Filed:
Jan. 28, 1997
Richard Joseph Saia, Schenectady, NY (US);
Bernard Gorowitz, Clifton Park, NY (US);
Kevin Matthew Durocher, Waterford, NY (US);
General Electric Company, Schenectady, NY (US);
Abstract
A method for fabricating a stack of circuit modules includes providing a plurality of substrates having module interconnection layers. Each of the substrates has a circuit chip with chip pads positioned therein and an electrically conductive feed-through line extending from a first surface of the substrate to a second surface of the substrate with the first surface being perpendicular to the second surface. Each of the module interconnection layers is situated over a respective first surface of each of the substrates and includes a module dielectric layer having module vias therein and a module pattern of electrical conductors extending through the module vias to couple the selected chip pads to the feed-through line. The plurality of substrates are stacked. A side interconnection layer is applied over a side surface including the second surfaces of the substrates. The side interconnection layer includes a side dielectric layer having side vias therein aligned with predetermined ones of the feed-through lines and a side pattern of electrical conductors extending through the side vias.