The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 1997

Filed:

Jun. 07, 1995
Applicant:
Inventors:

Geoffrey I Iswandhi, Sunnyvalea, CA (US);

William Edward Baker, Austin, TX (US);

William Patterson Bunton, Austin, TX (US);

John Deane Coddington, Cedar Park, TX (US);

Daniel L Fowler, Georgetown, TX (US);

David J Garcia, Los Gatos, CA (US);

Paul N Hintikka, Austin, TX (US);

Susan Stone Meredith, Hillsboro, OR (US);

Stephen H Miller, Round Rock, TX (US);

David Paul Sonnier, Austin, TX (US);

William Joel Watson, Austin, TX (US);

Frank A Williams, Austin, TX (US);

Assignee:

Tandem Computers Incorporated, Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395733 ; 39518501 ; 395736 ; 395741 ; 395742 ; 395824 ;
Abstract

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets, and stored at an interrupt queue in memory. Storage of the interrupt data will initiate an internal interrupt to notify the receiving CPU. The receiving CPU can then access the interrupt queue, examine the interrupt data, and determine what action to take.


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