The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 1997

Filed:

Sep. 15, 1995
Applicant:
Inventors:

Yukihiro Ushiku, Yokohama, JP;

Atsushi Yagishita, Yokohama, JP;

Satoshi Inaba, Tokyo, JP;

Minoru Takahashi, Yokohama, JP;

Masanori Numano, Yokohama, JP;

Yoshiki Hayashi, Yokohama, JP;

Yoshiaki Matsushita, Yokohama, JP;

Yasunori Okayama, Kawasaki, JP;

Hiroyasu Kubota, Yachiyo, JP;

Norihiko Tsuchiya, Tokyo, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257617 ; 257510 ; 257513 ; 257519 ; 257520 ; 257618 ; 257622 ; 257415 ; 257418 ;
Abstract

A semiconductor device has a semiconductor substrate having a groove, and a semiconductor element formed in a surface region of the semiconductor substrate. A substance having a thermal expansion coefficient different from the semiconductor substrate is embedded in at least a portion of the groove, a crystal defect is generated from the region near the bottom of the groove in the semiconductor substrate, thereby alleviating stress and strain in other regions of the semiconductor substrate, such that such regions cannot generate crystal defects in a region necessary for a circuit operation of the semiconductor element of the surface region.


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