The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 1997
Filed:
Oct. 04, 1996
So Wein Kuo, Hsin-Chu, TW;
Tsu Shih, Chakua, TW;
Taiwan Semiconductor Manufacturing Company, Ltd, Hsin-Chu, TW;
Abstract
A method to produce a contact or via opening and filled metallurgy for CMOS or other integrated circuits is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer structure is formed thereover comprising a first layer of tetraethoxysilane (TEOS), a second layer of borophospho-TEOS (BPTEOS), and a third layer of TEOS. A contact opening is etched through the insulating layer structure not covered by a mask to the semiconductor device structures to be electrically contacted wherein the profile of the contact opening is not vertical because the BPTEOS layer is etched. horizontally more than the first and third TEOS layers and wherein native oxide builds up on the sidewalls of the contact opening. The substrate is dipped into a hydrofluoric acid solution to remove the native oxide on the sidewalls of the contact opening whereby the hydrofluoric acid etches the BPTEOS layer at a slower rate than it etches the first and third TEOS layers whereby the contact profile is made vertical. A glue layer is sputter deposited over the surface of the insulating layer structure and within the contact opening. A conducting layer is deposited over the glue layer filling the contact opening completing the electrical contact in the fabrication of the integrated circuit device.