Failure memory device

Abstract

A failure memory device for compressing, in bit, failure data of a multi-bit memory under test to store the compressed failure data in a failure memory is provided, which is capable of generating a mask data. Failure data obtained from the logical comparison results of data written in a four bit memory under test are supplied to AND-OR circuits 27.sub.1 -27.sub.4 of a compression circuit 30 through input terminals 21.sub.1 -21.sub.4 respectively. In each AND-OR circuit, ANDs between the failure data and four bit compression data set in registers 26.sub.1 -26.sub.4 are performed respectively, and the ANDs are ORed. The ORed outputs of the respective AND-OR circuits are supplied to input pins 22.sub.1 -22.sub.4 of a failure memory 17. Readout data from output pins 23.sub.1 -23.sub.4 of the failure memory are supplied to AND-OR circuits 31.sub.1 -31.sub.4 of an expansion circuit 25 respectively. In the AND-OR circuit 31.sub.1, ANDs between the read out data and the first bit data of the registers 26.sub.1 -26.sub.4 are performed respectively and then the ANDs are ORed, and in the remaining AND-OR circuits 31.sub.2 -31.sub.4, ANDs between the read out data and the second bit data through the fourth bit data of the registers 26.sub.2 -26.sub.4 are performed respectively and the ANDs in each of the AND-OR circuits 31.sub.2 -31.sub.4 are ORed. The ORed outputs of the respective AND-OR circuits are supplied to output terminals 24.sub.1 -24.sub.4 as mask data.