The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 1997

Filed:

Jan. 30, 1996
Applicant:
Inventors:

Hironobu Niijima, Ohizumi-machi, JP;

Hiroshi Kawamoto, Menuma-machi, JP;

Akira Goishi, Kazo, JP;

Masayuki Kurihara, Gyoda, JP;

Toshimichi Iwai, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
324751 ; 364488 ;
Abstract

An IC fault analysis system which is capable of accurately correlating mask layout data and/or net listing data associated with CAD (computer aided design) data developed in the IC design and an image obtained by a non-contact type tester such as an electron beam tester. The IC fault analysis system includes a circuit diagram display for showing a circuit diagram of the IC device under test based on the CAD data, a mask layout display for showing a mask layout of the IC device under test based on the CAD data, a contrast image display for showing a potential distribution of the IC device under test obtained in the non-contact type tester, an input means connected to the circuit diagram display for specifying a circuit component of the IC device under test, a comparison means for comparing the circuit diagram of the circuit component defined by the input means and contrast image corresponding to the circuit component, and a comparison data memory for storing the comparison data of the comparison means and providing the comparison data to the contrast image display.


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