The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 1997

Filed:

Jul. 25, 1995
Applicant:
Inventors:

Jun-ichi Wada, Yokohama, JP;

Hisashi Kaneko, Fujisawa, JP;

Nobuo Hayasaka, Yokosuka, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438607 ; 438661 ; 438622 ;
Abstract

The method of manufacturing a semiconductor device, according to the present invention, includes the steps of forming a polycrystal lower-level Al wiring layer on a silicon substrate, forming an interlayer insulation film for covering the lower-level Al wiring layer on the entire surface, forming a connection hole which reaches the lower-level Al wiring layer in the interlayer insulation film, forming a polycrystal upper-level Al wiring layer on a surface of the interlayer insulation film, forming an interlayer insulation film for covering the upper-level Al wiring layer on the entire surface, and forming a single-crystal lower-level Al wiring layer and upper-layer Al wiring layer which are connected to each other in the connection hole by heating the silicon substrate so that the lower-level Al wiring layer and the upper-level Al wiring layer are converted from a polycrystal phase to an amorphous phase, and then cooling the silicon substrate so that the upper-level Al wiring layer is set in a supercooling state.


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