Sense amplifier circuitry for differential semiconductor memories

Abstract

A differential voltage memory apparatus is provided which includes one or more preliminary stages of differential amplifiers which operate prior to triggering of a final stage of differential amplifiers. The preliminary stages of differential amplifiers include cross-coupled inverters that are closely coupled to bit lines connected to memory cells of the memory apparatus. The final stage of sense amplifiers include cross-coupled inverters which are, in use, substantially decoupled from the bit lines of the memory cells. The preliminary sense amplifiers are activated shortly after activation of corresponding memory cells and provide an initial stage of amplification of a voltage differential generated by the memory cells. The final stage sense amplifiers are triggered after a suitable time delay guaranteeing that a sufficient minimum voltage differential has been generated. The preliminary sense amplifier stages, which are closely coupled to the bit lines and are thereby subject to heavy capacitive loading, provide an initial stage of amplification which is substantially immune from noise effects, such as effects caused by alpha strikes and the like. The final stage of sense amplifiers, which are substantially decoupled from the capacitive bit lines, coupled to quickly amplify the voltage differential to opposing rail voltages. The method and apparatus embodiments are described.