The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 22, 1997

Filed:

Mar. 11, 1994
Applicant:
Inventors:

Reza Kazerounian, Alameda, CA (US);

Rustom F Irani, Santa Clara, CA (US);

Boaz Eitan, Ra'anana, IL;

Assignee:

Waferscale Integration, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518516 ; 36523006 ; 36518513 ;
Abstract

An electrically programmable read-only memory (EPROM) array having self-aligned thick oxide isolation units, and a method for manufacturing the EPROM array are disclosed. The EPROM array is formed of EPROM areas having EPROM cells and control areas, two per EPROM area. Each control area includes at least one row and each row includes a first polysilicon strip, a second polysilicon strip lying on top of and perpendicular to the first polysilicon strip, and alternating thick and thin oxide elements under the first polysilicon strip. The thick and thin oxide elements are self-aligned to the first polysilicon strip. The thin oxide and the first and second polysilicon strips form a select transistor. The thick oxide and the first and second polysilicon strips form a novel self-aligned thick oxide isolation unit.


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