High density integrated circuit with bank select structure

Abstract

A high performance and high density integrated circuit includes interbank bitlines and a bank select structure which improve the vertical pitch of the integrated circuit layout and provide the selective access of data stored in the memory cells. The bank select structures includes bank select transistors which are located and oriented adjacent metal-to-diffusion region contacts such that vertical pitch of the layout is improved, thus promoting a higher density memory array. The bank select transistor is also formed such that conductivity is increased and impedance decreased due to a relatively wide channel width. On the substrate, a plurality of bitlines, including interbank bitlines and intrabank bitlines, and a plurality of wordlines are provided to form memory cells. In bank BK.sub.N, each interbank bitline extends into either bank BK.sub.N-1 or BK.sub.N+1 adjacent to bank BK.sub.N. For the selection of a cell or plurality of cells in bank BK.sub.N, bank BK.sub.N is selected first by applying bank select signals B.sub.N and B.sub.N+1 to bank select lines BSL.sub.N and BSL.sub.N+1, respectively, which activate respective bank select transistors. The desired column is selected by turning on respective column select transistors which are coupled to the sense amplifiers and readout circuits via column select lines and applying decode voltages to the selected column via the activated bank select transistors. Finally, the desired memory cell or cells within that selected column and bank BK.sub.N is selected with the plurality of left-right bit selector lines.