The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 1997

Filed:

Jun. 06, 1995
Applicant:
Inventors:

Janos Farkas, Austin, TX (US);

Rahul Jairath, Austin, TX (US);

Matt Stell, Folsom, CA (US);

Sing-Mo Tzeng, Austin, TX (US);

Assignees:

Sematech, Inc., Austin, TX (US);

Intel Corporation, Santa Clara, CA (US);

National Semiconductor Corp., Santa Clara, CA (US);

Digital Equipment Corp., Maynard, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437225 ; 437228 ; 1566451 ;
Abstract

A method of using additives with silica-based slurries to enhance metal selectivity in polishing metallic materials utilizing a chemical-mechanical polishing (CMP) process. Additives are used with silica-based slurries to passivate a dielectric surface, such as a silicon dioxide (SiO.sub.2) surface, of a semiconductor wafer so that dielectric removal rate is reduced when CMP is applied. The additive is comprised of at least a polar component and an apolar component. The additive interacts with the surface silanol group of the SiO.sub.2 surface to inhibit particles of the silica-based slurry from interacting with hydroxyl molecules of the surface silanol group. By applying a surface passivation layer on the SiO.sub.2 surface, erosion of the SiO.sub.2 surface is reduced. However, the metallic surface is not influenced significantly by the additive, so that the selectivity of metal removal over oxide removal is enhanced.


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