The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 5614427 B1

Date of Patent:

Mar. 25, 1997

Filed:

Jan. 20, 1995

Method of making an array of tfts having reduced parasitic capacitance

Applicant:

Inventors:

Willem den Boer, Troy, MI (US);

Mohshi Yang, Troy, MI (US);

Assignee:

OIS Optical Imaging Systems, Inc., Northville, MI (US);

Attorney:

Myers Liniak & Berenato

Primary Examiner:

Tom Thomas

Assistant Examiner:

Lynne A Gurley

Int. Cl.

CPC ...

H01L / ;

U.S. Cl.

CPC ...

437 40 ; 437 41 ;

Abstract

A thin film transistor (TFT) array in an active matrix liquid crystal display (AMLCD) including a centrally located round source electrode completely surrounded by a substantially annular or circular shaped drain electrode. The geometric design of the TFT of this invention provides for a thin film transistor having a reduced parasitic capacitance and decreased photosensitivity. The TFTs of this invention are located at the intersections of gate and drain lines of an active matrix LCD array thereby increasing the size of the pixel display openings of the matrix array.

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den Boer, Willem. (1997). Method of making an array of tfts having reduced parasitic capacitance (U.S. Patent No. 5614427). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5614427

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