The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 1997

Filed:

Feb. 24, 1995
Applicant:
Inventors:

Yinon Degani, Highland Park, NJ (US);

Thomas D Dudderar, Chatham, NJ (US);

Byung J Han, Scotch Plains, NJ (US);

Alan M Lyons, New Providence, NJ (US);

King L Tai, Berkeley Heights, NJ (US);

Assignee:

Lucent Technologies Inc., Murray Hill, NJ (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257723 ; 257777 ; 257778 ;
Abstract

Described is a novel packaging of MCM tiles without wire-bond interconnections and in a total thickness which is reduced relative to conventional MCM packaging. The MCM tile includes a substrate with a plurality of peripheral metallizations and at least one chip flip-chip mounted on the substrate. The PWB is provided with an aperture which is smaller than the size of the silicon substrate but larger than the outside dimensions of the mounted chips. The substrate is positioned on the PWB so that its ends overlap areas of the PWB adjacent the aperture and the chips fit into the aperture. Peripheral metallizations on the substrate are interconnected to metallizations on the PWB by either solder reflow technology or conductive adhesive technology.


Find Patent Forward Citations

Degani, Yinon. (1997). Packaging multi-chip modules without wire-bond interconnection (U.S. Patent No. 5608262). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5608262

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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