The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 11, 1997
Filed:
Dec. 16, 1993
Nobuyoshi Fujimaki, Tokyo, JP;
Shin-Etsu Handotai Co., Ltd., Tokyo, JP;
Abstract
A process and apparatus for manufacturing MOS devices are disclosed. The process comprises the step of controlling a first clearance linear speeds (1st CLSs) X which is the flows of an oxidizing and an annealing gases defined as ratios of the flow rates thereof to the area of a clearance between a semiconductor wafer and the interior surface of the tube of a heat treating furnace to be at least 30 cm/min while the semiconductor wafer is oxidized and annealed. The process comprises the step of controlling a second clearance linear speed (2nd CLS) Y which is a flow of the annealing gas defined as a ratio of the flow rate thereof to the area of the clearance to be at least 100 cm/min while the semiconductor wafer is taken out of the tube. The process comprises the step of controlling a relation between the 1st CLSs X and the 2nd CLS Y so that Y.gtoreq.-2.5 X+275. The process and the apparatus reduce and control the fixed-charge density in the oxide film of a MOS device with a high repeatability.