The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 1997
Filed:
Jun. 07, 1995
Shoji Wada, Tokyo, JP;
Kanehide Kenmizaki, Kodaira, JP;
Masaya Muranaka, Akishima, JP;
Masahiro Ogata, Ohme, JP;
Hidetomo Aoyagi, Tachikawa, JP;
Tetsuya Kitame, Kodaira, JP;
Masahiro Katayama, Ohme, JP;
Shoji Kubono, Akishima, JP;
Yukihide Suzuki, Akishima, JP;
Makoto Morino, Akishima, JP;
Sinichi Miyatake, Hamura, JP;
Seiichi Shundo, Hatoyama-machi, JP;
Yoshihisa Koyama, Hamura, JP;
Nobuhiko Ohno, Tokorozawa, JP;
Hitachi, Ltd., Tokyo, JP;
Hitachi ULSI Engineering Corp., Tokyo, JP;
Abstract
A defect remedy LSI mounted on a memory module, comprising: an input interface portion for capturing address and control signals, the input interface portion being the same as that of a dynamic RAM; an input/output interface portion corresponding to a data bus of a memory device comprised of a plurality of dynamic random access memories; a memory circuit to which a chip address and an X defective address of any of the plurality of random access memories are electrically written, the memory circuit being substantially made nonvolatile; a redundancy remedy RAM portion composed of a static RAM wherein a word line is selected by a compare match signal between an X address signal and the defective address of the memory circuit, the X address signal and the defective address being captured via the input interface portion, and a column is selected by a Y address signal captured via the input interface portion; a selecting portion for connecting a data input/output bus of the redundancy remedy RAM portion to an input/output circuit corresponding to a defective chip address; a data input/output portion for selectively activating an input/output circuit to be connected to a data bus corresponding to a dynamic RAM found defective; and a mask portion for outputting a control signal for putting in a high-impedance state an output pin of the defective RAM in a read operation.