The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 1996
Filed:
Sep. 06, 1995
Narayanan Meyyappan, Camas, WA (US);
Tatsuo Nakato, Vancouver, WA (US);
Abstract
The method is a technique for making silicon-on-insulator (SOI) wafers which are suitable for use in the production of CMOS devices, which are designed to operate with low power and low voltage. The method of the invention provides high quality SOI material at relatively low cost by implanting, in one form of the invention, a very low dose of nitrogen or oxygen ions at a very low energy into silicon, and thereafter diffusing oxygen during an annealing process to form a continuous buried layer of silicon-oxy-nitride (Si.sub.x,O.sub.y N.sub.z, or SON) or SiO.sub.2. The process includes using an ion beam to implant ions into the substrate, thereby damaging a region of the crystal. The feed gas for the ion beam may be a variety of nitro-oxide gases, such as NO, N.sub.2 O, NO.sub.2, as well as a simple mixture of nitrogen and oxygen gases. Other elemental ions may be implanted to create the desired crystal defects. The wafer is then annealed in an atmosphere that allows the diffusion of the second species, usually oxygen, through an upper layer of the substrate to the region wherein the crystal has been damaged, wherein the second species reacts with the damaged crystal material to form a thin layer of insulating material which is located a very small distance below the surface of the wafer.