Ieee std. 1149.1 boundary scan circuit capable of built-in self-testing

Abstract

An IEEE Std. 1149.1 boundary scan circuit which is capable of performing built-in self-testing includes a logic circuit, cascaded input boundary-scan cells that form an input boundary-scan register connected to input nodes of the logic circuit, cascaded output boundary-scan cells that form an output boundary-scan register connected to output nodes of the logic circuit, and a test access port system for controlling operation of the input and output boundary-scan cells. The test access port system provides a built-in self-test control signal to the input and output boundary-scan cells when executing built-in self-testing. The input boundary-scan register is reconfigurable to operate as a test pattern generator that provides test patterns to the logic circuit for a predetermined number of clock cycles upon receipt of the built-in self-test control signal. The output boundary-scan register is reconfigurable to operate as an output response analyzer that is driven by the logic circuit for the predetermined number of clock cycles upon receipt of the built-in self-test control signal. A family of input and output boundary-scan cells that can be reconfigured as a linear feedback shift register and as a multiple-input shift register is also disclosed.