The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 1996
Filed:
Mar. 02, 1995
Koushik Banerjee, Chandler, AZ (US);
Debendra Mallik, Chandler, AZ (US);
Ashok Seth, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An integrated circuit package which has internal bonding pads that are located on bonding shelves and coupled to internal conductive power/ground planes by conductive strips that extend along the edges of the shelves. The edge strips eliminate the need for conventional vias to couple the bonding pads to the planes and thus reduce the cost and size of the package and improve package electrical performance (less inductive, less resistance path). The bonding pads are coupled to an integrated circuit that is mounted to a heat slug attached to a top surface of the package. The heat slug can function as both a ground path and a thermal sink for the integrated circuit. The package may have capacitors coupled to the internal routing of the package to reduce the electrical noise of the signals provided to the integrated circuit. Additionally, the package may have multiple power planes dedicated to different voltage levels. The bonding pads and conductive planes are coupled to landing pads located on a bottom surface of the package. Attached to the landing pads are solder balls which can be soldered to an external printed circuit board.