The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 1996
Filed:
Jan. 04, 1995
Applicant:
Inventors:
Jerzy Kolinski, Portland, OR (US);
John Sprietsma, Hillsboro, OR (US);
Stephen Pawlowski, Beaverton, OR (US);
Henry Schaechterle, Hillsboro, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395306 ;
Abstract
An equal length symmetric computer bus topology. The equal length symmetric computer bus topology provides a bus signal path to a number of bus nodes. Each bus signal path extends from each node on the computer bus to a central junction point. The bus signal paths are of equal length and have identical electrical characteristics. The equal length symmetric computer bus topology minimizes the effect of transmission line reflections upon the bus signals. The equal length symmetric computer bus topology also causes very little clock skew.