The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 1996

Filed:

Mar. 15, 1995
Applicant:
Inventors:

Suresh V Golwalkar, Folsom, CA (US);

Richard Foehringer, Fair Oaks, CA (US);

Michael Wentling, Cameron Park, CA (US);

Ryo Takatsuki, Ibaraki-ken, JP;

Shigeo Kawashima, Kitakyusyu, JP;

Keiichi Tsujimoto, Kitakyusyu, JP;

Nobuaki Sato, Kitakyusyu, JP;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257676 ; 257723 ; 257666 ; 257686 ; 257777 ; 257786 ;
Abstract

A method is disclosed for constructing a dual-sided chip package onto a leadframe having a die pad and a set of lead fingers corresponding to the die pad. Integrated circuit dies are disposed onto each side of the die pad while the leadframe is supported with support blocks having cavities that accept the integrated circuit dies and that support each lead finger and that provide clearance for stitch bonds of the previously formed wire bonds. Thereafter, a one step plastic mold is formed around each assembly comprising the dual integrated circuit dies, the die pads, and the wire bonds.


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