The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 1996

Filed:

Feb. 16, 1994
Applicant:
Inventors:

David G Love, Pleasanton, CA (US);

Larry L Moresco, San Carlos, CA (US);

William Tai-Hua Chou, Cupertino, CA (US);

David A Horine, Los Altos, CA (US);

Connie M Wong, Fremont, CA (US);

Solomon I Beilin, San Carlos, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; B44C / ;
U.S. Cl.
CPC ...
1566431 ; 1566551 ; 1566561 ; 1566331 ; 216 13 ; 216 18 ; 216 33 ; 437180 ; 437209 ;
Abstract

Methods of constructing a wire interconnect structure on a substrate are described. The methods broadly comprise the steps of depositing a spacer layer on a surface of the substrate, depositing a mask layer on the spacer layer, and removing a first portion of the mask layer overlying a desired area on the substrate surface to expose the spacer layer underlying the first portion of the mask layer. The methods further comprise the step of etching the structure such that a first portion of the spacer layer overlaying the desired area is removed and such that a portion of the desired area is exposed, and the step of depositing a first conductive material on the exposed portion of the desired area such that a conductive post is formed on the substrate surface and mounted to the desired area. Some of the disclosed methods comprise additional steps for forming an interconnect structure on the opposite surface of the substrate and providing an electrical interconnect means between the two interconnect structures. Additionally, some of the disclosed methods comprise steps for forming fillets around the conductive post at the substrate surface.


Find Patent Forward Citations

Loading…