The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 1996
Filed:
Jan. 18, 1995
Aiman H El-Maleh, Montreal, CA;
Wojciech P Maly, Pittsburgh, PA (US);
Thomas E Marchok, Latrobe, PA (US);
Janusz E Rajski, West Montreal, CA;
Carnegie Mellon University, Pittsburgh, PA (US);
Abstract
Test pattern generation for a sequential logic circuit having combinational logic elements and sequential elements (D flip-flops) is enhanced in generation time and test pattern quality by first transforming the circuit to simplify the circuit for test pattern generation. In one embodiment the retiming transformation is used in which sequential elements are moved across combinational logic elements to increase the ratio of the total number of states which are traversable, and thus simplify the circuit for test pattern generation. The test set generated is equally applicable to the transformed test circuit as well as the manufactured circuit.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile