The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 1996

Filed:

Oct. 27, 1992
Applicant:
Inventors:

Peter E Freiermuth, Hyde Park, NY (US);

Kathleen S Ginn, Shelburne, VT (US);

Jeffrey A Haley, Raleigh, NC (US);

Susan J Lamaire, Yorktown Heights, NY (US);

David A Lewis, Carmel, NY (US);

Gavin T Mills, Burlington, VT (US);

Timothy A Redmond, Essex Junction, VT (US);

Yuk L Tsang, Hopewell Junction, NY (US);

Joseph J Van Horn, Underhill, VT (US);

Alfred Viehbeck, Fishkill, NY (US);

George F Walker, New York, NY (US);

Jer-Ming Yang, Changhwa City, TW;

Clarence S Long, Essex Junction, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05B / ; G01R / ;
U.S. Cl.
CPC ...
219678 ; 219704 ; 219710 ; 437174 ; 437248 ; 148D / ;
Abstract

The described invention is directed to microwave methods for burning-in, electrical stressing, thermal stressing and reducing rectifying junction leakage current in fully processed semiconductor chips individually and at wafer level, as well as burning in and stressing semiconductor chip packaging substrates and the combination of a semiconductor chip mounted onto a semiconductor chip packaging substrate. Microwaves burn-in devices in a substantially shorter period of time than conventional burn-in techniques and avoid the need for special workpiece holders which are required by conventional stress and burn-in techniques. Additionally, microwave methods are described for reducing the leakage current of recitfying junctions, such as PN junctions and Schottky barrier diode junctions of semiconductor devices on fully processed semiconductor chips and wafers.


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