The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 1996
Filed:
Nov. 10, 1993
David G Love, Pleasanton, CA (US);
Larry L Moresco, San Carlos, CA (US);
David A Horine, Los Altos, CA (US);
Wen-chou V Wang, Cupertino, CA (US);
Richard L Wheeler, San Jose, CA (US);
Patricia R Boucher, Mountain View, CA (US);
Vivek Mansingh, Santa Clara, CA (US);
Fujitsu Limited, , JP;
Abstract
A compact, reliable, and efficient cooling system for semiconductor chips is disclosed. In one embodiment, a plurality of semiconductor chips have their active surfaces mounted to a major substrate which provides electrical connections among the chips, and a cooling channel is formed above the major substrate and each chip for conducting a cooling fluid over the back surface of the chips. To increase cooling efficiency, heat sink arrays are formed on the back surfaces of the chips, each array including a plurality of heat conducting elements attached to the back surface. The arrays may be readily and inexpensively constructed with photo-lithography or wire bonding techniques. To control the flow of cooling fluid around the chip edges and to prevent cavitation of the cooling fluid a cavitation and flow control plate disposed at the bottom surface of the cooling channel and formed around the edges of the chips is included. With the increased cooling efficiency, the height of each cooling channel may be substantially reduced to allow close stacking of interconnect substrates for three-dimensional packages and to shorten the vertical communication time between the interconnect substrates.