Method of manufacture of high coupling ratio single polysilicon floating

Abstract

A MOSFET semiconductor, erasable programmable ROM device on a lightly doped semiconductor substrate comprising field oxide regions in the semiconductor substrate. The field oxide regions extends down into sunken regions in the substrate through the openings. At least one of the field oxide regions is removed from the substrate to provide an opened one of the sunken regions in the substrate below the removed one of the field oxide regions. Ion implanted regions lie in the substrate below the openings. A gate oxide layer over the opened sunken region, and a floating gate over the gate oxide layer. Preferably, a tunnel oxide region is formed on the surface of the device with the floating gate overlying the tunnel oxide region to form an EEPROM device. The exposed sunken region has a V-shaped cross section sunken region extending deep into the substrate.