Capacitive coupling configuration for an intergrated circuit package

Abstract

The present invention provides capacitive and/or power supply decoupling for an integrated circuit package by utilizing an externally mounted bypass capacitor between power and ground. The bypass capacitor is mounted on internal leads projecting into a cove area formed at one or both ends of an integrated circuit package whereby one such internal lead is connected to the external power lead and the other such internal lead is connected to the external ground lead. A flexible, high-temperature adhesive material is used to secure the capacitor to the internal leads in the cove of the IC package so that when the package is later subject to soldering temperature thereby softening the solder connections between internal leads and the capacitor, the capacitor will not be electrically or physically disconnected from the internal leads. The adhesive secures the capacitor in place until the high temperatures dissipate and the solder joints between capacitor and the internal leads harden. A second cove formed at the opposite end of the integrated circuit package allows integrated circuit packages to be stacked alternately, one on top of another, so the cove portion of each integrated circuit package provides clearance for the capacitor mounted immediately above or below each respective stacked integrated circuit package. In this manner, an ultra high density integrated circuit package comprising stacked discrete integrated circuit packages can be formed and capacitively decoupled.