The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 1996
Filed:
Mar. 09, 1993
Satoshi Meguro, Hinode, JP;
Kiyofumi Uchibori, Hachioji, JP;
Norio Suzuki, Koganei, JP;
Makoto Motoyoshi, Hachioji, JP;
Atsuyoshi Koike, Kokubunji, JP;
Toshiaki Yamanaka, Houya, JP;
Yoshio Sakai, Shiroyama, JP;
Toru Kaga, Urawa, JP;
Naotaka Hashimoto, Hachioji, JP;
Takashi Hashimoto, Hachioji, JP;
Shigeru Honjou, Kodaira, JP;
Osamu Minato, Hinode, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. A wiring line, formed as a separate conductive layer, is provided in the stacking arrangement of the drive and load MISFETs of a memory cell for applying a ground potential to source regions of the drive MISFETs thereof.