Field effect transistor without spacer mask edge defects

Abstract

A field effect transistor which is not susceptible to mask edge defects at its gate spacer oxides. The transistor is formed upon a (100) silicon semiconductor substrate through successive layering of a gate oxide, and a gate electrode. A pair of gate spacer oxides is then formed covering opposite edges of the gate oxide and the gate electrode. A screen oxide is then formed over the surface of the semiconductor substrate, the gate and the gate spacer oxides. The upper surface of the screen oxide has an angle of elevation not exceeding 54.44 degrees with respect to the semiconductor substrate. The screen oxide also smoothly flows from thicker regions at the junctures of the gate spacer oxides and the semiconductor substrate to thinner regions over the surface of the semiconductor substrate. The semiconductor substrate adjoining the gate spacer oxides is then ion implanted through the screen oxide to form amorphous source/drain electrodes. The penetration depth of the ion implant is greater than the thickness of the thinner regions of the screen oxide and no greater than the thickness of the thicker regions of the screen oxide. Finally, the amorphous source/drain electrodes are annealed. In a second embodiment, a dopes glass screen layer is used in place of the screen oxide layer. The glass layer must be removed prior to annealing the amorphous source/drain electrodes.