The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 1995
Filed:
Mar. 19, 1993
John M Caywood, Sunnyvale, CA (US);
Alan B Helffrich, III, San Francisco, CA (US);
Yervant D Lepejian, Palo Alto, CA (US);
Semiconductor Diagnosis & Test Corporation, Milpitas, CA (US);
Abstract
An automated system for identification of fabrication defects that lead to the failure of IC products. Design information of the product to be tested is analyzed to identify electrical node-to-node faults that can be caused by fabrication defects. The circuit is then analyzed to determine the electrical response to input patterns which result from the node-to-node faults. A matrix which relates failure responses to a multiplicity of input patterns as a function of process defects is constructed. This response matrix is used to identify the fabrication defect. In those cases in which the response matrix is degenerate, i.e. a set of output responses can arise from more than one fault, knowledge about the probability of occurrence of various defects is used to assign probabilities to the node-to-node faults which may generate the output response set. The system then takes knowledge of a specific IC test system and the response matrix to generate a set of test vectors to analyze a product. The system instructs the IC test system to apply these vectors to the device under test (DUT). The response of the DUT to the test vectors is used to identify the fabrication defect which caused the device to fail. Test results for a number of devices may be used to generate statistical measures which can be employed to improve the manufacturing process, thereby increasing yield.