The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 1995

Filed:

Aug. 19, 1994
Applicant:
Inventors:

Howard S Goad, Austin, TX (US);

Derick J Wristers, Austin, TX (US);

James H Hussey, Jr, Austin, TX (US);

Michael A Hillis, Austin, TX (US);

William C Chapman, Austin, TX (US);

Assignee:

Advanced Micro Devices, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B32B / ;
U.S. Cl.
CPC ...
428209 ; 428210 ; 428901 ; 428195 ;
Abstract

A photolithography test structure is provided for measuring the amount of notching associated with photolithography processing. The test structure includes a curved insulating structure placed in close spaced proximity with a conductive, interconnect structure. A pair of conductive pads are deposited at opposite ends of the interconnect structure for measuring the resistance through the interconnect. Depending upon the amount of notching associated with the interconnect, resistance readings will vary. Test areas containing notched interconnect can be compared with controlled areas specifically designed not to have notching in order to determine relative changes in resistance, and to correlate that resistance with notching magnitude. The insulating structure, interconnect structure and conductive pads are processed upon the same substrate material containing the resulting product requiring testing.


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