The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 1995
Filed:
Apr. 05, 1994
Larry L Byers, Apple Valley, MN (US);
Donald W Mackenthun, Fridley, MN (US);
Philip J Fye, Maplewood, MN (US);
Gerald J Maciona, Mounds View, MN (US);
Jeff A Engel, Chisago City, MN (US);
Ferris T Price, deceased, late of Mayer, MN (US);
Dale K Seppa, New Brighton, MN (US);
Unisys Corporation, Blue Bell, PA (US);
Abstract
A method for comprehensively testing embedded RAM devices and a means for detecting if any of the cells within the embedded RAM devices have a slow write recovery time. The preferred mode of the present invention utilizes built-in self-test (BIST) techniques for testing the embedded RAM's within a VLSI device. In accordance with the present invention, a modified 5N march test sequence is performed on the embedded RAM devices. The modified 5N March test sequence is a simple algorithm implemented in programmable hardware that has the capability of ensuring that the embedded RAM devices are functional and that they meet the recovery time requirements. The preferred mode of the present invention uses this algorithm to determine if the embedded RAMs are operating properly before the VLSI devices are used in card assembly. However, this method can also be used after card assembly to monitor the embedded RAM's integrity.