Two step etch back spin-on-glass process for semiconductor planarization

Abstract

A new method for forming a planarized dielectric layer on a patterned conducting layer was accomplished. The method involves forming a insulating layer over a semiconductor substrate having semiconductor devices and elevated areas, created by an array of DRAM storage cells, formed therein. A metal conducting layer is deposited and then patterned by etching. The patterned conducting layer is used to make the electrical connections to the device contact. A barrier insulator is deposited on the patterned conducting layer and then a spin-on-glass is deposited by several coatings to fill the recesses in the patterned conducting layer and planarize the surface. A two step etch back process is then used to further planarize the layer and remove the spin-on-glass from the conducting layer surface. The process is designed to avoid over etching into the patterned conducting layer at the edges of the elevated regions of the DRAM, where the spin-on-glass is by its very nature thin.