The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 1995
Filed:
Dec. 03, 1993
Hiroaki Saeki, Yamanashi, JP;
Teruo Asakawa, Yamanashi, JP;
Noboru Masuoka, Yamanashi, JP;
Masaki Kondo, Yamanashi, JP;
Tokyo Electron Limited, Tokyo, JP;
Abstract
The plasma etching apparatus for a semiconductor wafer includes a susceptor provided in the vacuum process chamber. An electrostatic chuck for attracting and holding the wafer is provided on the susceptor. The electrostatic chuck comprises a chuck electrode provided on the susceptor via an insulative layer. The chuck electrode is connected to the positive terminal of the DC power supply via a switch. The chuck electrode is coated with a resistive layer, and the wafer is placed directly on the resistive layer. The resistive layer exhibits an electric resistivity of 1.times.10.sup.10 .OMEGA..multidot.cm to 1.times.10.sup.12 .OMEGA..multidot.cm in a temperature range for etching. The resistive layer is formed to have such a surface roughness that a center line average hight falls within a range of 0.1 to 1.5 .mu.m. When the potential of the positive terminal of the DC power supply is applied to the chuck electrode, and the wafer is grounded via plasma, a contact potential difference is created between the surface of the resistive layer and the rear surface of the wafer, generating an electrostatic attractive force, so that the wafer is attracted and held by the resistive layer.