Method of manufacturing a new dram capacitor structure having increased

Abstract

A method for fabricating a stacked storage capacitor on a dynamic random access memory (DRAM) cell with increased capacitance was accomplished. The stacked capacitor is used with a field effect transistor (FET) as part of a dynamic random access memory (DRAM) cell for storing data in the form of stored charge on the capacitor. The method for making the capacitor involves forming a bottom electrode from a single polysilicon layer having a fin-shaped structure, and then using a second polysilicon layer and a plasma etch back to create a second self-aligned fin-like structure that significantly increases the surface area of the capacitor bottom electrode. The capacitor structure is then completed by forming a thin capacitor dielectric layer on the bottom electrode and depositing a third polysilicon layer to form the top electrode and complete the capacitor with significantly increased capacitance and an economy of processing steps.