The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 1995

Filed:

Jun. 06, 1994
Applicant:
Inventors:

Gary Hong, Hsin-Chu, TW;

Chen-Chiu Hsue, Hsin-Chu, TW;

H J Wu, Hsin-Chu, TW;

Lawrence Y Lin, Cupertino, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 61 ; 437 62 ; 437974 ; 148D / ; 148D / ;
Abstract

A method for forming a thin, uniform top silicon layer using bonded-wafer SOI technology is described. A dielectric layer is formed on a first surface of a first silicon substrate. A trench is formed in a first surface of a second silicon substrate. A polishing stopper is formed in the trench. A second dielectric layer with a smooth top surface is formed over the polishing stopper and over the first surface of the second silicon substrate. The smooth top surface of the second dielectric layer of the second silicon substrate is bonded to the dielectric layer of the first silicon substrate. Material is removed from the exposed surface of the second silicon substrate to form the silicon layer with well-controlled thickness, having a top surface co-planar with the polishing stopper.


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