The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 1995

Filed:

Sep. 30, 1993
Applicant:
Inventor:

Tong-Chern Ong, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365185 ; 365 63 ; 365104 ; 365174 ;
Abstract

A method and device to compensate for the series resistance effect along, for example, the source region in an electrically programmable read only memory array is described. One or more resistors are provided between the ground contact and ground. When a cell is programmed, the source is coupled to ground through one or more of the resistors, such that the resistance between source and ground for all cells is approximately equal. Therefore, the potential of the source of each cell is approximately equal for all cells during programming. In this way, the potential difference between the control gate and source is approximately equal for every cell, thereby resulting in more uniform programming levels and therefore more uniform threshold voltages. The method and device of the present invention is particularly applicable to multi-level cells, which employ several different threshold voltages to represent several different logic states. In addition to providing for uniform threshold voltages, the resistors of the present invention can be used to provide for programming to different levels using a single programming voltage on the control gate. For each level, the source of a cell is coupled to ground through one or more resistors, such that the potential difference between the control gate and the source has the appropriate value for that level.


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