Process for forming arrayed field effect transistors highly integrated

Abstract

A process for forming an array of FATMOS transistors serving as memory cells of a NAND cell type EEPROM. A multi-layered structure is provided on a substrate with two stacked conductive layers insulated by an intermediate insulative layer, the first or inner conductive layer being insulated by a first insulative layer from the substrate, the second or outer conductive layer being covered with a second insulative layer. The second insulative layer is etched to define a first array of etched layer portions. A photoresist layer is deposited and etched to define a second array of layer portions, each of which is positioned between two neighboring ones of the first array of layer portions. The multi-layered structure is etched with the first and second layer portions being as a mask, to thereby form an array of a plurality of pairs of insulated gate electrodes above the substrate. A chosen impurity is doped into the substrate with the insulated gate electrodes serving as a mask to thereby form impurity-doped regions in the substrate.