The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 20, 1994
Filed:
May. 24, 1994
United Microelectronic Corporation, Hsinchu, TW;
Abstract
A new method of local oxidation by means of forming a plurality of silicon trenches is described. Portions of the insulating layer over the surface of a silicon substrate not covered by a mask pattern are etched through exposing the portion of the silicon substrate that will form the device isolation region. A first trench is etched into the exposed portion of the substrate. A layer of silicon nitride is deposited over the insulating layer and within the trench. A layer of an aluminum-silicon alloy is deposited overlying the silicon nitride layer. The aluminum-silicon layer is etched away whereby silicon nodules are formed on the surface of the silicon nitride layer. The nodules are oxidized to form silicon dioxide nodules. Using the silicon dioxide nodules as a mask, the silicon nitride layer is etched through to the insulating layer where it exists and to the silicon substrate surface where it is exposed and a set of narrow trenches is etched into the exposed portions of the substrate. The silicon substrate within the set of trenches is oxidized wherein the silicon is transformed to silicon dioxide and the silicon dioxide expands to fill the set of trenches. The silicon nitride layer and the silicon dioxide nodules within the opening are pushed up to align with the silicon nitride layer and the silicon dioxide nodules on either side of the opening. The remaining insulating layer and silicon nitride layer are removed wherein the silicon dioxide nodules are also removed completing the device isolation of the IC.