The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 1994

Filed:

Sep. 14, 1993
Applicant:
Inventors:

Steven J Hillenius, Summit, NJ (US);

William T Lynch, Summit, NJ (US);

Lalita Manchanda, New Providence, NJ (US);

Mark R Pinto, Morristown, NJ (US);

Sheila Vaidya, Watchung, NJ (US);

Assignee:

AT&T Corp., Murray Hill, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257357 ; 257397 ; 257508 ; 257514 ; 257520 ; 257622 ;
Abstract

Through the use of a specifically configured buried dielectric region, devices with strict design rules, e.g., design rules of 0.9 micrometers and less, are significantly improved. In particular, the recessed dielectric region, e.g., field oxide, separating device areas in an integrated circuit, either has a buried conducting shield surrounding the periphery of the oxide or has a configuration such that the upper surface of the dielectric is no more than 20 nm below the upper surface of the silicon forming the device active region. By insuring a suitable configuration, parasitic capacitance resulting in slower operation is considerably reduced while leakage currents are maintained at an acceptable level.


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