The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 1994
Filed:
Nov. 30, 1992
James D Hayden, Austin, TX (US);
James R Pfiester, Austin, TX (US);
Hsing-Huang Tseng, Austin, TX (US);
Motorola Inc., Schaumburg, IL (US);
Abstract
A semiconductor device (10) and process provides first and second, electrically coupled MOS transistors (14, 16) in which the current gain of the second MOS transistor (16) is greater than the current gain of the first MOS transistor (14). First and second gate structures (23, 25) are formed on a gate dielectric layer (26) overlying a semiconductor substrate (12). The gate dielectric layer (26) has a uniform thickness in all regions. The current gain differential between the first and second MOS transistors (14, 16) is obtained by selectively forming a dielectric intrusion layer (42) under the gate structure (23) of the first MOS transistor (14), whereas the dielectric layer (26) underlying the gate structure (25) of the second MOS transistor (16) retains the uniform thickness. The dielectric intrusion layer (42) causes a higher channel resistance in the first MOS transistor (14) which retards the current gain in the first MOS transistor (14) relative to the current gain of the second MOS transistor ( 16).