Gate circuit, semiconductor integrated circuit device and method of

Abstract

A novel gate circuit is disclosed. A first semiconductor switch includes a couple of main terminals connected between a first potential level and an output node, in which a high impedance state is held in response to an input signal having a first logic level and a second logic level, and the impedance state changes from high to low only during a transient period when the input signal changes substantially from the first to second logic level. A second semiconductor switch includes a couple of main terminals inserted between a second potential level different from the first potential level and the output node, in which a high impedance state is held in response to the input signal, and the impedance state changes from high to low only during a transient period when the input signal changes from the second to first logic level.