The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 1994
Filed:
Jul. 31, 1992
Harshvardhan P Sharangpani, Santa Clara, CA (US);
Jonathan B Sweedler, Sunnyvale, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A data register file system is provided in a microprocessor having a pipelined execution unit that employs the data register file to store operands and results of its instruction executions. The data register file system includes a plurality of data registers, each of which stores one of the operands and results. A pointer table has a plurality of pointer registers, each storing an address of one of the data registers. A first address generation logic is coupled to the pointer table and the pipelined execution unit for generating a first set of pointer table addresses to access a first group of the pointer registers for the addresses of a first group of the data registers which are required by the execution of a first floating point instruction. The first address generation logic services the first floating point instruction A second address generation logic is coupled to the pointer table and the pipelined execution unit for generating a second set of pointer table addresses to access a second group of the pointer registers for the addresses of a second group of the data registers which are required by the execution of a second instruction. The second address generation logic is provided specifically to facilitate the issue and execution of the second floating point instruction in parallel with the first floating point instruction The second instruction is an exchange instruction that requires an exchange of contents stored in the second group of data registers. A circuit is coupled to the pointer table and the data registers for coupling the addresses of the first group of the data registers to the data registers for accessing the first group of the data registers. A read circuit is coupled to the pointer table for reading the addresses of the second group of the data registers. An exchange circuit is coupled to the read circuit for exchanging the addresses read from the second group of the pointer registers and writing the addresses exchanged back to the second group of the pointer registers. The second instruction is issued and executed in parallel with the first instruction. A method of executing the exchange instruction in parallel with other instructions in the data register file system is also described.