The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 1994
Filed:
May. 07, 1993
Sun-Chieh Chien, Taipei, TW;
Yu-Ju Liu, Hsin-Chu City, TW;
United Microelectronics Corporation, Hsinchu, TW;
Abstract
A method of removing impurities from the surface of an integrated circuit and forming a uniform thin native oxide layer on the same surface of an integrated circuit is described. A hydrofluoric acid solution, followed by a rinse and spin dry, is often used to remove gate oxide from within an opening etched in a polysilicon layer. The rinsing leaves water spots. Spin drying leaves impurities where water tracks were. An H.sub.2 O.sub.2 cleaning is performed to remove the water spots. After the cleaning, a uniform thin layer of native oxide is formed on the surface of the silicon substrate. A second layer of polysilicon is deposited over this first thin native oxide layer and doped with an implant dosage chosen so that it will go through the uniform native oxide layer. The substrate is annealed to drive in the buried contact. Processing continues to form polysilicon or silicide gate electrodes. Source and drain regions are formed within the openings to the silicon substrate between the gate electrodes. Spacers are formed on the sidewalls of the gate electrodes. An insulating layer is deposited over the surface of the silicon substrate. Contact openings are etched through the insulating layer to the second polysilicon layer and to the silicon substrate. A metal layer is deposited over the insulating layer and filling the openings to the second polysilicon layer and the silicon substrate. The metal layer is patterned, completing the formation of the buried contacts within the integrated circuit.