The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 1994

Filed:

Oct. 30, 1992
Applicant:
Inventors:

Dean L Frew, Garland, TX (US);

Mark A Kressley, Richardson, TX (US);

Arthur M Wilson, Richardson, TX (US);

Juanita G Miller, Richardson, TX (US);

Philip E Hecker, Jr, Garland, TX (US);

James Drumm, Crystal Lake, IL (US);

Randall E Johnson, Houston, TX (US);

Rick Elder, Houston, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K / ;
U.S. Cl.
CPC ...
361784 ; 361760 ; 361785 ; 361792 ; 361813 ; 174 521 ; 174255 ; 439 68 ; 257686 ; 257697 ;
Abstract

The multi-chip circuit module of the invention comprises a plurality of circuit chips assembled in a laminated stack. Each chip includes a plurality of layers of thin film interconnect patterns in the normal configuration, except for the final layer or layers, which comprise a reroute pattern that locates all circuit input and output pads along a single edge of each chip. The relocated pads are provided with contact bumps to facilitate the addition of a bonded lead to each I/O pad extending therefrom to a point beyond the edge of each chip. Thus, upon lamination the protruding tips form an array of leads on a single lateral face of the laminated chip stack.


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