Circuitry for power supply voltage detection and system lockout for a

Abstract

A detection circuit is described that resides in a nonvolatile memory that includes a memory array and a control circuitry coupled to the memory array for controlling operations of the memory array. The detection circuit is coupled to the control circuitry and receives a power supply for detecting potential level of the power supply and for generating a reset signal to reset the control circuitry until the potential level of the power supply rises above a predetermined level. The detection circuit includes a resistor, a first, a second, and a third transistor. The first transistor has a first end coupled to receive the power supply, a second end coupled to a first node, and a third end coupled to the first node. The second transistor has a first end coupled to the first node, a second end coupled to ground, and a third end coupled to the ground. The first and second transistors function as a voltage divider. The third transistor has a first end coupled to the power supply, a second end coupled to an output node, and a third end coupled to the first node. The resistor is coupled between the output node and the ground for coupling the output node to the ground when the third transistor is not conducting, and for providing a positive potential at the output node when the third transistor is conducting. When the power supply has not reached the predetermined level, the third transistor is not conducting and the output node outputs the reset signal that is a ground potential. When the power supply rises above the predetermined level, the third transistor starts to conduct and the output node registers the positive potential and ceases generating the reset signal. The first, second, and third transistors are of the same channel type such that the circuitry operates substantially independent of process variations and temperature variations.