The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 1994

Filed:

May. 07, 1993
Applicant:
Inventors:

Water Lur, Taipei, TW;

J Y Wu, Dou-Lio, TW;

Jenn-Tarng Lin, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 53 ; 437933 ; 437941 ; 437985 ;
Abstract

A new method of fabricating a convex charge coupled device is achieved. A silicon oxide layer is formed over the surface of a silicon substrate and patterned with a charge coupled device (CCD) electrode mask to provide openings to the silicon substrate. Nitride spacers are formed on the sidewalls of the openings. The integrated circuit is coated with a spin-on-glass layer. After curing, the spin-on-glass layer is etched back to expose the nitride spacers. Removing the nitride spacers leaves a second set of openings to the silicon substrate. Ions are implanted into the substrate through the second set of openings. The oxide layer is removed. The wafer is globally oxidized resulting in a thermal oxide layer with undulatory thickness. The thermal oxide is removed leaving a convex surface on the silicon substrate. A gate oxide layer is formed on the convex surface of the silicon substrate. A polysilicon layer is deposited overlying the gate oxide layer and patterned to form gate electrodes to complete formation of the charge coupled device.


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